Jose Pineda de Gyvez

As the complexity of integrated circuits advances toward submicron technologies with high transistor densities in the order of 10 elements, the integration between process technology and system design becomes a relevant issue. This book addresses the study of process and design variables in order to determine the ease and feasibility of fabrication—or manufacturability—of contemporary Very LargeScale Integration (VLSI) systems and circuits. The book will introduce the reader to key aspects in today's design practices. The four topics shown in Figure 1.1—yield modeling, defect and fault modeling, testing, and fault tolerant architectures—are intended to link common interests to both design and process engineers. The whole manufacturing process from circuit to silicon will be examined, with each subject supporting each other. For instance, the use of yield modeling will be examined to foresee the IC's feasibility of fabrication. This will be followed by the study of manufacturing defects and their impact on circuit design, and will be complemented with the implementation of strategies for fault tolerant architectures. Integrated circuit (IC) manufacturability has received a great deal of attention in recent years. As technological processes are advancing toward submicron resolution features—with higher transistor integration on silicon taking place—the need to foresee the ease and feasibility of fabrication of IC designs is becoming essential. IC manufacturability is no longer a practice that belongs exclusively to industry [1]. Today it is a flourishing area of academic research in which systematic solutions are sought for yield-related problems. This presents a dramatic departure from the previous practice of ad hoc research to address such problems. The result of this interaction is the emergence of methodologies for yield and fault prediction, taking into account existing manufacturing conditions.